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SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
SDA
SCL
S
S TART condition
P
STO P condition
Figure 30. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a register read cycle.
ACKNOWLEDGE CYCLE
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiving device.
The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter
releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver
must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the
high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to
receive the next byte.
“ACKNOWLEDGE AFTER EVERY BYTE” RULE
The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge
signal after every byte received.
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
ADDRESSING TRANSFER FORMATS
Each device on the bus has a unique slave address. The LP5521 operates as a slave device with the 7-bit
address. LP5521 I 2 C address is pin selectable from four different choices. If 8-bit address is used for
programming, the 8th bit is 1 for read and 0 for write. In the following table is represented the 8-bit I 2 C
addresses.
ADDR_SEL
[1:0]
00
01
10
11
I 2 C address write
(8 bits)
0110 0100 = 64H
0110 0110 = 66H
0110 1000 = 68H
0110 1010 = 6AH
I 2 C address read
(8 bits)
0110 0101 = 65H
0110 0111 = 67H
0110 1001 = 69H
0110 1011 = 6BH
Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device
should send an acknowledge signal on the SDA line, once it recognizes its address.
The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends
on the bit sent after the slave address — the eighth bit.
When the slave address is sent, each device in the system compares this slave address with its own. If there is a
match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the
R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.
24
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